The present invention relates generally to logic circuits and, more particularly, to charge recycling differential logic circuits.
With the emergence of an electronics market that stresses portability, compact size, lightweight and the capability for prolonged remote operation, a demand has arisen for low power circuits and systems. This demand has motivated circuit designers to depart from conventional circuit designs and venture into more power and space efficient alternatives. As part of this effort, charge recycling differential logic has emerged as an important design tool for increasing power efficiency.
FIG. 1A shows a prior art charge recycling differential logic circuit 100A and associated prior art control circuit 100B. As seen in FIG. 1A, prior art charge recycling differential logic circuit 100A required six transistors: PFET 105, PFET 107, NFET 109, NFET 115, NFET 117 and NFET 121. Prior art charge recycling differential logic circuit 100A also included differential logic 123 with control variable inputs 151 and 153, pass variable inputs 155 and 157, output 111 and outBar 113. In addition, PFET 105 and PFET 107 of prior art charge recycling differential logic circuit 100A included back biasing inputs 131 and 133 having a voltage Vbb applied.
As discussed below, prior art charge recycling differential logic circuit 100A also required control circuit 100B. Control circuit 100B included three additional transistors: PFET 137; PFET 135; and NFET 139. Prior art control circuit 100B also included an enable out signal (eout) at terminal 143. According to the prior art, the control signal eout, at terminal 143 was supplied to a prior art charge recycling differential logic circuit 100A as control signal ein at terminal 119 as discussed below.
In FIG. 1A, prior art charge recycling differential logic circuit 100A and associated prior art control circuit 100B are shown separately for simplicity and clarity. However, in practice prior art charge recycling differential logic circuit 100A and associated prior art control circuit 100B are combined in a single circuit. FIG. 1B shows one combination of prior art charge recycling differential logic circuit 100A and associated prior art control circuit 100B into the resulting prior art charge recycling differential logic circuit 100C. As shown in FIG. 1B, prior art charge recycling differential logic circuit 100C required nine transistors: PFET 105, PFET 107, NFET 109, NFET 115, NFET 117, NFET 121, PFET 137; PFET 135; and NFET 139. Prior art charge recycling differential logic circuit 100C also included differential logic 123 with control variable inputs 151 and 153, pass variable inputs 155 and 157, output 111 and outBar 113. In addition, PFET 105 and PFET 107 of prior art charge recycling differential logic circuit 100C included back biasing inputs 131 and 133 having a voltage Vbb applied. Prior art charge recycling differential logic circuit 100C also included an enable out signal (eout) at terminal 143. According to the prior art, the control signal eout, at terminal 143 was supplied to a following prior art charge recycling differential logic circuit (not shown) as control signal ein at a corresponding input terminal as discussed below.
As discussed above, prior art charge recycling differential logic circuit 100C required an enable in (ein) signal, coupled to the gate of NFET 121. The control signal ein was supplied by a prior art control circuit, similar to prior art control circuit 100B in FIG. 1A, of the previous stage. When multiple prior art charge recycling differential logic circuits 100C were cascaded together, prior art control circuit 100B and control signal ein was necessitated to ensure that each prior art charge recycling differential logic circuit 100C switched or xe2x80x9cfiredxe2x80x9d only after it had received an input from the previous stage.
As noted above, when multiple prior art charge recycling differential logic circuits 100C were cascaded together, each prior art charge recycling differential logic circuit 100C required prior art control circuit 100B to ensure that each prior art charge recycling differential logic circuit 100C switched or xe2x80x9cfiredxe2x80x9d only after it had received an input from the previous stage. However, prior art control circuit 100B added significant complexity to prior art charge recycling differential logic circuit 100C, requiring at least three additional transistors and several circuit lines. Consequently, prior art charge recycling differential logic circuit 100C required significant additional components and space. This, in turn, meant that prior art charge recycling differential logic circuit 100C required more silicon, a more complex design, more components to potentially fail and more components to produce heat.
In addition, prior art control circuit 100B not only added complexity to prior art charge recycling differential logic circuits 100C, but it also loaded the output nodes 111 and 113 of prior art charge recycling differential logic circuit 100C and drew current from output nodes 111 and 113 of prior art charge recycling differential logic circuit 100C to charge the control signal ein. In addition, in the prior art, if prior art control circuit 100B were made small, the control signal ein was slow, and this slowed down the operation of prior art charge recycling differential logic circuit 100C. Consequently, there was pressure to increase the size of prior art control circuit 100B. However, Increasing the size of prior art control circuit 100B to speed up the control signal ein also increased the loading on the output nodes 111 and 113 of prior art charge recycling differential logic circuit 100C and therefore slowed down the evaluation of logic 123.
What is needed is a method and apparatus for creating charge recycling differential logic that does not require the complex control circuitry of prior art charge recycling differential logic circuits and is therefore simpler, more space efficient and is more reliable than prior art charge recycling differential logic circuits.
According to the invention, the prior art control circuitry is eliminated. The clocked charge recycling differential logic circuit of the invention is instead activated from a delayed clock. According to the invention, when clocked charge recycling differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked charge recycling differential logic circuit of the invention. Each delayed clock is timed to at least the delay of the previous clocked charge recycling differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked charge recycling differential logic circuit of the invention is switched or xe2x80x9cfiredxe2x80x9d only after it has received an input from the previous clocked charge recycling differential logic circuit.
According to the invention, clocked charge recycling differential logic circuits do not require the significant additional components used in the prior art. This, in turn, means that the clocked charge recycling differential logic circuits of the invention require less space, are simpler, dissipate less heat and have fewer components to potentially fail. In addition, clocked charge recycling differential logic circuits of the invention eliminate the loading of the output nodes of the charge recycling differential logic circuit since there is no control signal ein, and therefore no prior art control circuits to draw current from the output nodes to charge the control signal ein. Consequently, using the clocked charge recycling differential logic circuits of the invention, speed is increased because there is less loading on the output nodes and the clocked charge recycling differential logic circuit of the invention can start evaluating once a differential voltage develops between the inputs coming from the previous clocked charge recycling differential logic circuit.
In particular, one embodiment of the invention is a cascaded chain of clocked charge recycling differential logic circuits. The chain includes a first clocked charge recycling differential logic circuit. The first clocked charge recycling differential logic circuit includes: a first clocked charge recycling differential logic circuit clock input terminal; at least one first clocked charge recycling differential logic circuit data input terminal; and at least one first clocked charge recycling differential logic circuit data output terminal.
The cascaded chain also includes a second clocked charge recycling differential logic circuit. The second clocked charge recycling differential logic circuit includes: a second clocked charge recycling differential logic circuit clock input terminal; at least one second clocked charge recycling differential logic circuit data input terminal; and at least one second clocked charge recycling differential logic circuit data output terminal.
According to the invention, the at least one first clocked charge recycling differential logic circuit data output terminal is coupled to the at least one second clocked charge recycling differential logic circuit data input terminal to form the chain. According to the invention, a first clock signal is coupled to the first clocked charge recycling differential logic circuit clock input terminal and a second clock signal is coupled to the second clocked charge recycling differential logic circuit clock input terminal. According to the invention, the second clock signal is delayed with respect to the first clock signal by a predetermined delay time.
In one embodiment of the invention, a delay circuit is coupled between the first clocked charge recycling differential logic circuit clock input terminal and the second clocked charge recycling differential logic circuit clock input terminal to provide the predetermined delay time.
One embodiment of the invention is a clocked charge recycling differential logic circuit that includes a clocked charge recycling differential logic circuit out terminal and a clocked charge recycling differential logic circuit outbar terminal.
In one embodiment of the invention, the clocked charge recycling differential logic circuit also includes a first node, the first node is coupled to a first supply voltage.
In one embodiment of the invention, the clocked charge recycling differential logic circuit also includes a first transistor, the first transistor including a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode. The first node is coupled to the first transistor first flow electrode and the first transistor second flow electrode is coupled to the clocked charge recycling differential logic circuit out terminal. The first transistor also includes a back bias input terminal having a back bias voltage thereon.
In one embodiment of the invention, the clocked charge recycling differential logic circuit also includes a second transistor, the second transistor including a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode. The first node is coupled to the second transistor first flow electrode and the second transistor second flow electrode is coupled to the clocked charge recycling differential logic circuit outBar terminal.
In one embodiment of the invention, the clocked charge recycling differential logic circuit also includes a third transistor, the third transistor including a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode. The first transistor control electrode is coupled to the third transistor first flow electrode and the clocked charge recycling differential logic circuit outBar terminal. The second transistor control electrode is coupled to the third transistor second flow electrode and the clocked charge recycling differential logic circuit out terminal. The third transistor control electrode is coupled to the clock signal.
In one embodiment of the invention, the clocked charge recycling differential logic circuit also includes a fourth transistor, the fourth transistor including a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode. The first transistor second flow electrode is coupled to the fourth transistor first flow electrode. The fourth transistor second flow electrode is coupled to a second node. The fourth transistor control electrode is coupled to the third transistor first flow electrode and the clocked charge recycling differential logic circuit outbar terminal.
In one embodiment of the invention, the clocked charge recycling differential logic circuit also includes a fifth transistor, the fifth transistor including a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode. The second transistor second flow electrode is coupled to the fifth transistor first flow electrode. The fifth transistor second flow electrode is coupled to the second node. The fifth transistor control electrode is coupled to the third transistor second flow electrode and the clocked charge recycling differential logic circuit out terminal.
In one embodiment of the invention, the clocked charge recycling differential logic circuit also includes a sixth transistor, the sixth transistor including a sixth transistor first flow electrode, a sixth transistor second flow electrode and a sixth transistor control electrode. The sixth transistor first flow electrode is coupled to the second node and the sixth transistor second flow electrode is coupled to a second supply voltage. A delayed clock signal is coupled to the sixth transistor control electrode of the clocked charge recycling differential logic circuit.
In one embodiment of the invention, the clocked charge recycling differential logic circuit also includes a logic block, the logic block including at least one logic block control variable input terminal, a logic block out terminal and a logic block outBar terminal. The logic block out terminal is coupled to the clocked charge recycling differential logic circuit out terminal and the logic block outBar terminal is coupled to the clocked charge recycling differential logic circuit outBar terminal.
As discussed in more detail below, the method and apparatus of the invention for creating charge recycling differential logic does not require the complex control circuitry of prior art charge recycling differential logic circuits and is therefore simpler, saves space and is more reliable than prior art charge recycling differential logic circuits. As a result, the clocked charge recycling differential logic circuits of the invention are better suited to the present electronics market that stresses portability, compact size, lightweight and the capability for prolonged remote operation.
It is to be understood that both the foregoing general description and following detailed description are intended only to exemplify and explain the invention as claimed.